www.iterrac.com IT4050D dual lvds-to-scfl level translator this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4051 rev 0 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 description features absolute maximum ratings the IT4050D is a wideband lvds-to-scfl level translator fabricated using 0.1 m hbt gaas technology. it is based on ecl topology to guaran tee high-speed operation. the two translators are fully independent, allowing power consumption to be optimized according to the application. the device can translate nrz streams with data rate up to 3.125 gb/s or clock signals with a frequency up to 3.125 ghz. the inputs and outputs of the IT4050D are dc coupled. at the input side, internal 100-ohm resistors between the two differential lines avoid the need for external impedance matching terminations. the input levels ar e fully compliant with lvds specifications. the IT4050D uses scfl output levels and allows either single ended or differential data output. the excellent rise and fall time and the good quality of the eye diagram at all data rates up to 3.125 gb/s makes the IT4050D suitable for interfacing a ge neric lvds output buffer with all iterra scfl parts. ? wideband signal handling: up to 3.125 gb/s nrz ? input sensitivity: 350 mv differential ? 450 mv pp typical single-ended output ? jitter rms: <2 ps ? output rise time (20% ? 80 %): <55 ps oc 150 -65 storage temperature t stg oc 125 -15 operating temperature range - die t a v 2.4 0 input voltage level, low level v il v 2.4 0 input voltage level, high level v ih v 0 -3.63 power supply voltage v ee v 2.75 0 power supply voltage v dd units max. min. parameters/conditions symbol stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ? output fall time (20% ? 80 %): <55 ps ? 100-ohm (differential) matched dc-coupled inputs ? 50-ohm matched dc-coupled outputs ? differential or single-ended output ? power consumption: 140 mw per translator
www.iterrac.com IT4050D dual lvds-to-scfl level translator this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4051 rev 0 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 electrical characteristics v 1.22 dc input voltage (with dc-coupled input) v indc v 1.05 input voltage level, low level (single ended) v il v 1.4 input voltage level, high level (single ended) v ih v -3.3 negative power supply voltage v ee v 2.5 positive power supply voltage v dd oc 85 0 operating temperature range ? die t a units max. typ. min. parameters/conditions symbol recommended operating conditions ma 36 negative power supply current (5) i ee ma 8 positive power supply current (5) i dd ps 2 rms jitter (4) j rms ps 12 peak-to-peak jitter (4) j p-p db 15 output return loss (up to 7 ghz) s 22 ps 55 output fall time (20%-80%) t f ps 55 output rise time (20%-80%) t r mv -450 output voltage level, low level (single ended) v ol v 0 output voltage level, high level (single ended) v oh mv 450 data output voltage amplitude (3 ) v out v 1.22 dc input voltage (with dc-coupled input) (2) v indc mw 140 power dissipation (5) p d v 1.05 input voltage level, low level (single ended) v il v 1.4 input voltage level, high level (single ended) v ih v -3.3 negative power supply voltage v ee v 2.5 positive power supply voltage v dd units typ. parameters/conditions symbol 1. electrical characteristics at ambient temperature. 2. in case of single- ended input the unused pin has to be tied to vindc. 3. in case of single- ended output, the unused pad must be terminated with 50 ohms to ground. 4. on a 3-gb/s prbs pattern, dc coupled output. 5. current and power dissipation are per converter.
www.iterrac.com IT4050D dual lvds-to-scfl level translator this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4051 rev 0 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 timing diagram eye diagram performance die measurements (out and out/) vdd: +2.5 v, vee: -3.3 v input data rate: 3 gb/s differential data input (1.1 v/0.6 v) with two separated 50-ohms to ground termination, dc-coupled output device diagram
www.iterrac.com IT4050D dual lvds-to-scfl level translator this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4051 rev 0 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 recommended operational setup recommended chip mounting chip size: 1400 m 10 m x 2900 m 10 m chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m
www.iterrac.com IT4050D dual lvds-to-scfl level translator this is a production data sheet. se e ?product status definitions? on web site or catalog for product development status. october 5, 2005 doc. 4051 rev 0 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 pad positions and chip dimensions chip size: 1400 m 10 m x 2900 m 10 m chip thickness: 104 m 3 m pad size: 100 m x 100 m rf pad pitch: 150 m
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